1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a nonvolatile memory device and a method of forming the same. Further, the invention relates to an electrically erasable and programmable read only memory (EEPROM) device in various types of non-volatile memory devices retaining data even when a power source is cut off, and a method of forming the same.
2. Description of the Related Art
The semiconductor memory device can be largely classified into a random access memory (RAM) and a read only memory (ROM). The RAM is a volatile memory device in which stored data disappears when a power supply is interrupted. The ROM is a nonvolatile memory device in which stored data is retained even if the power supply is interrupted. The ROM includes an EEPROM device capable of electrically programming and erasing information.
FIG. 1 is a sectional view of a related art EEPROM in which a unit cell includes a non-volatile memory device and a selection device. In the related art EEPROM, a memory device 20 and a selection device 30 have stacked gate structures 19a and 19b, respectively. That is, the stacked gate structure 19a of the memory device 20 includes a floating gate 14a, an inter-gate insulation layer 16a, and a control gate 18a sequentially stacked on a substrate 10 having a silicon oxide layer 22 formed thereon. Likewise, the stacked gate structure 19b of the selection device 30 includes a bottom electrode 14b, an inter-gate insulation layer 16b, and a top electrode 18b sequentially stacked on the substrate 10 having the silicon oxide layer 22. In the stacked gate structure 19b of the selection device 30, the top electrode 18b and the bottom electrode 14b are electrically connected to each other by a butting contact. A floating junction 24 is formed in the substrate 10 between the stacked gate structure 19a of the memory device 20 and the stacked gate structure 19b of the selection device 30 to connect the memory device 20 and the selection device 30. A drain region 13 of the memory device 20 is formed as a bit line junction at a side of the stacked gate structure 19a opposite to the floating junction 24. Additionally, a source region 12 is formed as a source junction of the selection device 30 at a side of the stacked gate structure 19b opposite to the floating junction 24. In the memory device 20, programming and erasing may be performed using Fowler-Nordheim (FN) tunneling. The selection device 30 is formed to select a memory device or to prevent over-erasing of the memory device.
In a manufacturing process of the related art EEPROM, a silicon oxide layer, a polysilicon layer, an inter-gate insulation layer, and a polysilicon layer are sequentially stacked on the substrate 10. Then, photolithography is performed to form the stacked gate structures 19a and 19b, which are spaced apart from each other. An ion implantation process is performed to form the floating junction 24 between the stacked gate structures 19a and 19b, and to form the drain region 13 and the source region 12 outside the stacked gate structure.
In the related art EEPROM structure, the distance between the memory device 20 and the selection device 30 is determined by the resolution of photolithography equipment. Accordingly, there is a limitation in reducing a unit cell size. Additionally, unlike in the stacked gate structure 19a of the memory device 20, it is necessary to connect electrically the bottom electrode 14b and the top electrode 18b in the stacked gate structure 19b of the selection device 30. To accomplish this, a butting contact process is required which limits reducing the chip size and complicates the overall fabrication.